NanoWatt Design™ was formed early in 2011 to commercialize ultra-low power SCL circuit architecture. The company's patent-pending, asynchronous, SCL architecture promises dramatic reduction in power consumption of digital circuitry, while meeting requirements for speed. The new Sleep Convention Logic (SCL) technology is delay insensitive, making it very robust to variation. Additionally, NanoWatt Design can provide software that extends industry standard design tools for use in creating asynchronous SCL circuits.
Relative to standard CMOS, SCL promises >100X reduction in standby leakage power and >7X reduction in energy per operation.
Applications for SCL include:
- LOW POWER, HIGH SPEED devices such as GPS, net books, net tops, smart books, smart phones, digital still cameras, digital TV, digital set-top box, networking, encryption, video and image processing;
- LOW POWER, LOW SPEED devices such as Smart cards, RFID, environmental and agricultural monitoring, (i.e. drought, insects, contamination), homeland security (i.e. border motion, radiation sensing), wild-land fire prediction & detection, AND medical implants.
- Especially relevant for mobile electronics devices where battery life is a key concern.
Advantages of SCL include:
- Ultra-low power, with every logic gate “put to sleep” following every single operation, and only awakened to respond to data.
- Delay-insensitive (DI) such that process variation, supply voltage and temperature changes affect speed, but otherwise circuits continue to operate normally. Difficulties with maintaining circuit timing are avoided.
- Seamlessly transitions from high speed, ultra-low power to low speed, even-lower power, as supply voltage is dropped! Operation has been proven at energy-optimal 0.3 volts.
- Performance (speed) is comparable to synchronous circuits.
- Compatible with readily available EDA tools developed for synchronous circuits. Minimal training required!