nanoWatt Design™ was formed early in 2011 to commercialize asynchronous circuit architectures. The company has multiple proprietary, asynchronous, architectures that provide opportunities for reduction in both active and standby leakage power consumption of digital circuitry. The company has capability for implementing Sleep Convention Logic (SCL), Null Convention Logic (NCL), Bundled Delay (BD), and Globally Asynchronous Locally Synchronous (GALS) architectures, as well as asynchronous controllers. NanoWatt Design has tools that enable efficient conversion of an existing circuit from synchronous to asynchronous. The several technology solutions are protected by combination of issued and pending patents.
nanoWatt works with both standard cell and custom libraries. SCL optionally makes use of a custom library, and promises 3 - 8x reduction in standby leakage power.
The company is currently focused on bringing to market a Sensor Hub solution operating in the range of 0.3 – 0.6 volts. The Sensor Hub is functionally similar to a microcontroller (MCU). nanoWatt is currently applying multiple patent-pending approaches to optimize a Sensor Hub design for lowest overall energy consumption.
Applications for ultra-low voltage circuits include devices such as Sensor Hubs, smart cards, RFID, environmental and agricultural monitoring, (i.e. drought, insects, contamination), homeland security (i.e. border motion, radiation sensing), wild-land fire prediction & detection, and medical implants.
Advantages of nanoWatt Design’s ultra-low voltage circuit solutions include:
- Optionally, every logic gate “put to sleep” following each operation, and only awakened to respond to data. This is a key advantage for low to moderate duty cycle applications.
- Speed insensitive circuits seamlessly transition from high speed, ultra-low power to low speed, even-lower power, as supply voltage is dropped.
- Performance (speed) is comparable to synchronous circuits.
- Compatible with readily available EDA tools developed for synchronous circuits.
- Multi-core operation optimized by first allowing each core to operate with an independent clock, then reducing voltage and frequency.