The patent-pending SSAS architecture is specifically targeted to multi-core processors, where each processor is allowed to operate “just as fast as it must”.

A multi-core processor array can be rapidly customized to meet specific user requirements.


 

Solutions

Tremendous progress has been made in improving SoC energy efficiency through the application of fundamental low power design techniques such as clock gating and voltage scaling. However, as SoC complexity has grown it has become increasingly difficult to squeeze further improvements from these techniques. NanoWatt has taken a fresh look at power efficiency and has developed techniques to achieve additional savings by focusing on SoC level issues.

Multi-Core Design and SSAS Technology

Many DSPs today utilize an array of cores - dozens to hundreds - to achieve overall performance goals through parallelization. However, power management of arrays of cores has lagged behind until now. NanoWatt has developed patent pending control and communication technology enabling voltage and frequency scaling (DVFS) of each of the cores independently of all the other cores, no matter how many cores there are. Double-digit energy improvements have been demonstrated over the entire array of cores for a challenging application. Since DVFS is programmable for each individual core, higher energy savings will be seen for lighter applications. This technology, termed Switchable Synchronous to Asynchronous dynamic voltage and frequency Scaling (SSAS), is scalable to any number of cores.

Communication Networks

On-chip communication networks, sometimes referred to as Networks on Chip (NoCs), have become increasingly important as overall SoC complexity has grown. The NoC can significantly impact overall SoC reliability, power consumption, and throughput. NanoWatt has applied asynchronous signaling technologies to NoC design, demonstrating simpler, faster operation. One key attribute of the Asynchronous NoC (ANoC) is that it does not require routing synchronizers. In typical SoC designs, hundreds or even thousands of synchronizers may be eliminated from the end design, leading to dramatic improvement in reliability (MTBF); reduction in power; and improvements in latency and area.

Energy-Efficient Architecture

Transistor and gate level optimizations are no longer sufficient for building energy-efficient designs. The major differentiation and advances today occur at the architecture level. Yet, building an effective and efficient architecture requires broad and deep knowledge in Low Power Design. NanoWatt has extensive experience in the many facets of Low Power Design that enable architectural optimizations for DSPs, communications processors, and wireless devices. This Low Power Design expertise has led to a variety of architecturally optimized designs, including for example an asynchronous floating point unit (FPU), a MSP430 microcontroller targeted at wireless sensor nodes, and a multi-core vision processor.