Sleep Convention Logic (SCL)
Technology Background
SCL delay insensitive circuits automatically adapt to changes in environmental and physical factors, and will run as fast as allowed by current conditions. For example, if supply voltage is reduced, SCL will simply slow down. By contrast, synchronous circuits must assume the worst case for environmental and physical factors, and designers must slow down the clock to ensure correct operation.
SCL evolved from and supersedes null convention logic (NCL), an asynchronous architecture relying on handshakes to maintain timing. The first patent on NCL was issued to Karl Fant in 1994. The original NCL proved to be somewhat sensitive to delays. Delay insensitive (DI) circuits began to appear in the mid-2000s. With DI, no assumptions are made on the delays of wires or gates. Progress on delay insensitivity sets the stage for adoption of asynchronous architecture.
Sleep Convention Logic (SCL)
Sleep Convention Logic (SCL) is a powerful asynchronous circuit architecture providing remarkable design flexibility and is an elegant solution for ultra low power, high speed circuitry. Rather than a simple combination of multi-threshold CMOS (MTCMOS) and NCL, SCL architecture has been optimized to incorporate sleep signals with minimal overhead, and performance meeting requirements. SCL has been shown to deliver dramatic power reduction relative to either NCL or any conventional synchronous design. Every logic gate is “put to sleep” following every single operation, and only awakened to respond to data. In addition to combinational logic, completion and registration blocks may also be put to sleep. And, in contrast to synchronous circuits that switch every clock cycle, SCL circuits only switch when useful work is being done. Since SCL is delay-insensitive (DI), process variation, supply voltage and temperature changes affect speed, but otherwise circuits continue to operate normally. Difficulties with maintaining circuit timing are avoided. SCL seamlessly transitions from high speed, ultra-low power to low speed, even-lower power, as supply voltage is dropped! Operation has been proven at 0.3 volts. Performance (speed) is comparable to synchronous circuits.
NanoWatt Design's Competitive Advantages
- SCL offers by far the lowest active power available for circuits requiring medium to high speed.
- SCL flexibly adapts from standard supply voltage to reduced voltage, delivering even lower power at the expense of speed. Although currently a secondary target market for the company, the low power, low speed capability of SCL is particularly important for energy harvesting applications, such as those used in devices for monitoring and sensing.
- SCL produces negligible electromagnetic interference (EMI).
- NanoWatt Design offers script-based customization of Synopsys and Mentor Graphics tools for easy synthesis of SCL gates. With the large number of transistors used in circuits today, automation of design is extremely important. Extending conventional synchronous design tools to asynchronous SCL design is a critical enabler for design automation that is not readily available with competitors.
- As industry progresses to smaller transistors and lower supply voltages, standby leakage power is increasingly important. SCL offers an elegant solution for controlling sleep mode without requiring a sleep management circuit.